Unlike conventional random access memory (RAM) chip technologies, in magnetic RAM (MRAM) data is not stored as electric charge, but is instead stored by magnetic polarization of storage elements. The storage elements are formed from two ferromagnetic layers separated by a tunneling layer. One of the two layers has at least one pinned magnetic polarization (or fixed layer) set to a particular polarity. The magnetic polarity of the other magnetic layer (or free layer) is altered to represent either a “1” (e.g., anti-parallel to the fixed layer) or “0” (e.g., parallel to the fixed layer). One such device having a fixed layer, a tunneling layer, and a free layer is a magnetic tunnel junction (MTJ). The electrical resistance of an MTJ is dependent on the magnetic polarity of the free layer compared to the magnetic polarity of the fixed layer. A memory device such as MRAM is built from an array of individually addressable MTJs.
FIG. 1 is a circuit schematic illustrating a portion of a conventional magnetic random access memory (MRAM). An MRAM 100 is divided into a number of bitcells 110, 140, 160. During read out of the bitcell 160, the resistance of the bitcell 160 is compared to the reference parallel bitcell 110 and the reference anti-parallel bitcell 140. Resistance of the bitcells 110, 140, 160 are measured by applying a source voltage and determining an amount of current flowing through the bitcells 110, 140, 160. For example, in the bitcell 110, a voltage source 120 is applied to a magnetic tunnel junction (MTJ) 112 by read select transistors 122, 124, and a word line select transistor 126. The MTJ 112 includes a fixed layer 114, tunneling layer 116, and a free layer 118. When the free layer 118 and the fixed layer 114 have magnetizations aligned substantially parallel, the resistance of the MTJ 112, and thus the bitcell 110, is low. When the free layer 118 and the fixed layer 114 have magnetizations aligned substantially anti-parallel, the resistance of the MTJ 112, and thus the bitcell 110, is high.
Bitcells of a magnetic random access memory may be arranged in one or more arrays including a pattern of memory elements (e.g. MTJ in case of MRAM). In order to achieve high-yielding memory arrays, it is critical to tightly control the size of memory elements. Previous design techniques for implementing large-scale memory arrays have been hampered by the macro-loading effect that are inherent in the etching process. For example, the etching rate of memory elements may be larger at the edge of arrays in comparison to the center of arrays because the pattern density is smaller at the edge. As a result, the size of an MTJ at the edge of a unit array block can be substantially different from the size of an MTJ near the center of the array block. This may causing reduced production yields.
Patterning a large number of uniformly sized memory cells in an large scale memory array such as an MRAM array may provide a uniform pattern density over a relatively large area and may increase production yields. The macro-loading effect may be reduced by providing large-scale arrays of uniformly sized memory cells so that a larger number of the memory cells reside in areas of uniform pattern density after etching. However, various design constraints and challenges have hampered development of large scale MRAM arrays with uniform pattern density.
Previously proposed methods for providing large-scale MRAM arrays have not provided for placement of signal distribution lines or circuitries within memory arrays. Signal distribution lines such as word line (WL) strapping and are needed in practical designs, for example to provide low-resistance signal paths to bitcells within a number of bitcell sub-arrays. Simple signal-boosting circuitry may be used instead of metal strapping. In addition, substrate ties may be placed periodically inside memory arrays to provide the bulk connection of access transistors in bitcells. Generally the width of WL strapping and substrate ties are minimized with applicable design rules to save area.
One method of providing placement of signal distribution lines in a large-scale memory array is described with reference to FIG. 2. The large-scale memory array 202 is divided into a number of sub-arrays 204 each of which includes a pattern of 64×64 bit cells, for example. To compensate for the macro loading effect at the edge of each sub-array, a number of dummy bit cells may be placed around the perimeter of each sub-array 204. These dummy bit cells can include non-functional memory cells, such as floating MTJs which are not connected to memory control circuitry. However, word line strapping and substrate ties may occupy areas that do not include MTJs.
In FIG. 2, the signal distribution lines or circuitry cause pattern discontinuities which affect overall pattern density of the array. Because the large scale arrays includes a large number of relatively small sub-arrays, this method generates a large number of pattern discontinuities to accommodate placement of signal distribution lines such as substrate ties or WL strapping. Although increasing the number of dummy cells may mitigate this problem, this approach is not economically practical because multiple lines of dummy cells in sub-arrays would dramatically increase the total chip size. Hence, in practical memory arrays, the minimal number of dummy memory cells may be placed, and their size may be relatively larger than that of active memory cells within the sub-arrays 204 to compensate for stronger loading effect at the edges of sub-arrays. However, this approach often results in considerable degradation of pattern uniformity.
Construction of large scale memory arrays with uniform pattern density throughout has been proposed to reduce the macro-loading effect and increase production yields. Such proposals have failed to address various design constraints and have not provided a method for placement of WL strapping or substrate ties, for example.